The present invention relates generally to a method and apparatus to permit a computer system to receive information while the CPU is in a sleeping state, and more particularly to a peripheral device with multiple modes of operation that facilitate receiving and buffering data while the computer""s CPU is in a sleeping or suspended state.
As mobile computing devices seek to extend time-of-operation between battery charges, power management has become increasingly important. One way in which power management is accomplished is by completely, or partially, shutting down computer components, such as the central processing unit (CPU), hard disk drive, display, and other input/output (I/O) devices, when the computer is not performing operations.
During some of these power management modes, also known as sleeping states, the computer""s CPU may cease communications with and control of its peripheral resources, including I/O components, and those resources may not be accessible to any other computer component. Such power management techniques are not unique to any one computer system architecture.
One hardware system specification, the Advanced Configuration and Power Interface (ACPI) Specification, by Intel, Microsoft, and Toshiba, Revision 1.0b, Feb. 2, 1999, provides enhanced power management in a personal computer (PC) system architecture. The ACPI Specification describes the transfer of power management functions from the Basic Input/Output System (BIOS) to the operating system, thereby enabling demand-based peripheral and power management. Through the application of this specification, PC computers manage power usage of peripheral devices such as CD-ROMs, network cards, hard disk drives, codecs, and printers, as well as consumer electronics connected to a PC, such as video cassette recorders, television sets, telephones, and stereos.
ACPI provides several low-power sleeping states, S1-S5, that reduce the power consumed by the platform by limiting the operations it may perform. These sleeping states are described in the table below; S0 has been added as an indicator of the xe2x80x98activexe2x80x99 or xe2x80x98no sleeping statexe2x80x99. These various operating states are herein referred to as power management states. xe2x80x98Contextxe2x80x99, as used in the table below, refers to variable data held by the CPU and other computer devices. It is usually volatile and can be lost when entering or leaving certain sleeping states.
In many computing architectures, including the PC computing architecture, data may only be transferred between two peripheral devices by having the host operating system manage such transfer. That is, the processing system or CPU, through one of its auxiliary components, functions as a xe2x80x9cmasterxe2x80x9d controlling the data flow to, from, and among peripheral devices which function as xe2x80x9cslavesxe2x80x9d. The xe2x80x9cmasterxe2x80x9d is also commonly referred to as the xe2x80x9cbus masterxe2x80x9d.
FIG. 1A is a system level diagram of a conventional computing architecture. Generally, the Processing System 100 acts as the xe2x80x9cmasterxe2x80x9d by directly or indirectly controlling communications to, from, and among peripheral devices 116,118, and 134. A component, such as the Processing System 100, which acts as the xe2x80x9cmasterxe2x80x9d for managing data flow is often also referred to as the xe2x80x9cdefault bus masterxe2x80x9d. The Processing System 100 is typically communicatively coupled to the peripheral devices 116, 118, and 134 via a bus 112. Often, an I/O Hub 130 is employed to couple the bus 112 the one or more peripheral devices 116, 118, and 134 and route data therebetween as indicated by the bi-directional dashed lines. The I/O Hub 130 and the peripheral devices 116, 118, and 134 are usually communicatively coupled by secondary buses 114, 120, and 132.
In most computing architectures, the peripheral devices 116, 118, and 134 cannot operate without the management of the Processing System 100. Thus, while the Processing System 100 is in certain power management states, such as a sleeping or suspended state, the peripheral devices 116, 118, and 134 may not transmit or receive data to or from the Processing System 100 or other peripheral devices.
In another example, FIG. 1B is a prior art, system-level diagram of relevant components of the PC computing architecture. In this architecture, the I/O Controller Hub (ICH) 180 manages communications to and from peripheral devices 166,168, 184 by controlling data flow to the Memory Controller Hub (MCH) 150. The bus between the ICH 180 and MCH 150 is known as the Hub Link bus 162. The MCH 150 may store data received from the ICH 180 in memory (RAM) 160 and the CPU 152 may access such data via the MCH 150.
The ICH 180 communicates with various peripheral devices 166,168,184 and I/O components via standard buses or interfaces. For instance, the computer""s hard disk drive (HDD) 168 may be coupled to the ICH 180 via an Integrated Drive Electronics (IDE) or Extended IDE (EIDE) interface 170. xe2x80x9cCoupledxe2x80x9d as used herein includes electrically coupling two or more components. The ICH 180 may also communicate with an audio codec (AC""97) 166 through the AC""97 Link 164. Other peripheral devices may also be interfaced with the ICH 130 through such interfaces as a Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), RS-232 serial port, or parallel port.
Regardless of the interface or peripheral device, the ICH 180 routes data, indicated by the dashed bi-directional lines, between said interface or device and the MCH 150 as indicated in FIG. 1B. The host computer""s operating system (OS) acts as the default Hub Link bus master when the CPU 152 is not in a sleeping state. A number of devices are capable of becoming bus masters, but only the main CPU 152 can serve as the default bus master. When the CPU 152 is in sleeping states S3-S5, the Hub Link bus 162 is not usually operable. That is, while the CPU 152 is in these sleeping states, its resources are often unavailable and communications with the computer and its peripheral devices is not generally possible without awakening the CPU 152. Typically, the ICH 180 is designed with a single Hub Link interface and can handle only one bus master.
One increasingly common peripheral component in mobile computers is a mobile communications device compatible with the Bluetooth Specification, v.1.0B, Dec. 1, 1999. The Bluetooth Specification is a communications standard for wireless communications between mobile PCs, mobile phones, and other portable devices. This standard makes possible the interconnection of a wide range of computing and telecommunications devices via ad hoc, short-range radio links.
Presently, most computers utilize external I/O devices to serve as Bluetooth-compliant transceivers. These devices are often connected to a computer via a Universal Serial Bus (USB) port or some other standard I/O interface. They also rely on the computers"" CPU to process the messages received and store them in memory. Therefore, these Bluetooth-compliant transceivers would not be able to operate during those times when the computers"" CPU is in a sleeping state. However, keeping the CPU powered just to enable the connectivity of Bluetooth-compliant devices is wasteful of the limited power available to mobile computers.
Accordingly, there is a need for a peripheral device to permit a host system to receive information while the processing system or CPU is in a sleeping state without disturbing the sleeping or suspended state of the processing system or CPU.